1. Field of the Invention
The present invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels.
The invention further relates to a multilevel memory device comprising a plurality of multilevel memory cells organized into sectors, the sectors being split into a plurality of data units wherein a programming operation is performed in parallel.
The invention relates, particularly but not exclusively, to a Flash memory device, and the following description is made with reference to this application field with the only aim of simplifying illustration.
2. Description of the Related Art
As it is well known, in the Flash memory field, the multilevel technique is now widely accepted as a means to increase data density, with an equal physical density of the memory cells.
Known are multilevel memory devices which can store several logic values in a single memory cell. These devices are made in the form of integrated electronic circuits, which have achieved a sufficient degree of reliability to allow their large scale production for several technical and commercial applications.
The market of semiconductor integrated electronic devices is showing great interest in multilevel memory devices because they can offer information storage densities which are at least double in comparison with two-level memory devices, both by using the same technology and the same circuit area occupation.
The operation of such multilevel memory devices will now be briefly described. The different programming state of a memory cell results in a different value of the threshold voltage Vth thereof.
Of course, for a two-level cell, there can be only two values, corresponding to a logic 0 and a logic 1 respectively. In this case, the amount of information that can be stored is equal to one bit per cell.
Instead, a multilevel memory cell can store more than one bit. From the electrical point of view, this results in more than two possible threshold voltage values. The amount of information that can be stored in a single multilevel cell increases according to the following relation:Number of bits per cell=log2(number of values of Vth)
From the physical point of view, the possibility of altering the threshold voltage Vth, and therefore of programming the multilevel memory cell, is realized by the floating gate structure of the transistor which form the memory cell. The gate region is DC-isolated but it can be accessed by charge injection processes of the Channel Hot Electrons and/or Fowler-Nordheim Tunneling Effect type.
When suitably controlled, these processes allow the amount of charge caught in the floating gate to be modulated, thereby allowing the effect of the latter on the threshold voltage Vth value to be changed.
The possibility of generating, in a large number of cells, a set of threshold voltage levels which can be distinguished from each other upon reading is thus used to increase the density of the stored data.
However, the multilevel technique has inherently the disadvantage of slowing the processes of reading and programming each cell.
Additionally, there are applications—e.g., the implementation of a FAT memory for disk-on-silicon embodiments—which require the writing of small amounts of data, usually at non-contiguous addresses, for which the programming times are significantly longer.
In fact these applications require, for data updating, erasing/programming cycles to be performed. Considering the time taken by such operations, two major problems stand out:
the updating time per bit becomes unacceptable if the amount of data to be updated is small;
an auxiliary memory is needed to store data not to be updated, which data are nevertheless erased, the erasing being carried simultaneously out on a whole sector.
These problems make the use of current Flash memory architectures improposable.
Furthermore, power consumption is critical to such applications: all the energy used to store data which require no updating, but which are involved in the erasing/programming process, is lost with respect to the updating operation.
Power usage is the more inefficient the smaller is the ratio between the data to be updated and the sector size.